Copyright © 2005 The Institute of Electronics, Information and Communication Engineers
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
1 The authors are with Renesas Technology Corp., Itami-shi, 664-0005 Japan. E-mail: noda.hideyuki{at}renesas.com, 2 The authors are with Hiroshima University, Higashi-Hiroshima-shi, 739-8527 Japan., 3 The author is with Waseda University, Kitakyushu-shi, 808-0135 Japan.
This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.
Key Words: CMOS, Ternary CAM, network, refresh
Manuscript received September 2, 2004. Manuscript revised November 15, 2004.