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IEICE Transactions on Electronics 2006 E89-C(6):819-822; doi:10.1093/ietele/e89-c.6.819
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Copyright © 2006 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit and Device Technologies -- Letters

Design of Analog Current-Mode Loser-Take-All Circuit

Mohsen ASLONI, Abdollah KHOEI and Khayrollah HADIDI

The authors are with the Microelectronic Research Laboratory, Department of Electrical Engineering, Urmia University, Urmia 57159, Iran. E-mail: st_m.asloni{at}mail.urmia.ac.ir, E-mail: a.khoei{at}mail.urmia.ac.ir, E-mail: kh.hadidi{at}mail.urmia.ac.ir

A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4xN MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias affects the threshold voltage of transistors and improves performance of the structure.

Key Words: loser-take-all, winner-take-all

Manuscript received November 2, 2005. Manuscript revised January 15, 2006.


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