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IEICE Transactions on Electronics 2008 E91-C(6):887-893; doi:10.1093/ietele/e91-c.6.887
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuits and Related SoC Integration Technologies - Papers

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

Tomohiko ITO1, Daisuke KUROSE1, Takeshi UENO1, Takafumi YAMAJI1 and Tetsuro ITAKURA1

1 The authors are with Mobile Communication Laboratory, Corporate Research and Development Center, Toshiba Corporation, Kawasaki-shi, 212-8582 Japan. E-mail: tomohiko2.ito{at}toshiba.co.jp


  Abstract

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.

Key Words: A/D, ADC, pipeline, low power, amplifier, pseudo-differential amplifier, I/Q sharing

Manuscript received October 23, 2007. Manuscript revised December 21, 2007.


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