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IEICE Transactions on Electronics 2008 E91-C(6):903-910; doi:10.1093/ietele/e91-c.6.903
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuits and Related SoC Integration Technologies - Papers

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

Yusuke OHTOMO1, Masafumi NOGAWA1, Kazuyoshi NISHIMURA1, Shunji KIMURA2, Tomoaki YOSHIDA2, Tomoaki KAWAMURA1, Minoru TOGASHI1 and Kiyomi KUMOZAKI2

1 The authors are with NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi-shi, 243-0198 Japan. E-mail: ohtomo{at}aecl.ntt.co.jp, 2 The authors are with NTT Access Network Service Systems Laboratories, NTT Corporation, Chiba-shi, 261-0023 Japan.


  Abstract

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

Key Words: PON, burst, CDR, IC, CID

Manuscript received October 11, 2007.


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