Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Special Section on Analog Circuits and Related SoC Integration Technologies - Papers |
Design of Low Power Track and Hold Circuit Based on Two Stage Structure
1 The authors are with the Graduate School of Science and Engineering, Tokyo Institute of Technology, Tokyo, 152-8552 Japan. E-mail: takahide{at}ec.ss.titech.ac.jp, 2 The author is with ROHM CO., LTD, Yokohama-shi, 222-8575 Japan.
This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.
Key Words: track and hold circuit, low power consumption, flash analog to digital converter, two-stage structure
Manuscript received October 23, 2007. Manuscript revised December 25, 2007.
References
[1] F. Liu, S. Jia, Z. Lu, and L. Ji, "CMOS folding and interpolating A/D converter with differential compensative T/H circuit," Proc. 2003 IEEE Conference on Electron Devices and Solid-StateCircuits, pp.453–456, 2003. [2] T. Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, and H. Okada, "4 GB/s track and hold circuit using parasitic capacitance canceler," Proc. European Solid-State Circuits Conference, pp.347–350, 2004. [3] A.N. Karanicolas, "A 2.7-V 300-MS/s track-and-hold amplifier," IEEE J. Solid-State Circuits, vol.32, pp.1961–1967, Dec. 1997. [4] D.A. Johns and K. Martin, Analog integrated circuit design, John Wiley & Sons, 1997. [5] Ruby van de Plassche, CMOS integrated analog to digital and digital to analog converters, Kluwer Academic Publishers, 2003. [6] I.H. Wang, J.L. Lin, and S.I. Liu, "5-bit, 10GSamples/s track-and-hold circuit with input feedthrough cancellation," Electron. Lett., vol.42, no.8, pp.457–459, April 2006. [7] M. Choi and A.A. Abidi, "A 6-b 1.3-Gsample/s A/D Converter in 0.35-µm CMOS," IEEE J. Solid-State Circuits, vol.36, pp.1847–1858, Dec. 2001. [8] K. Nagaraj, D.A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T.R. Viswanathan, "A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-µm digital CMOS process," IEEE J. Solid-State Circuits, vol.35, pp.1760–1768, Dec. 2000. [9] L.Y. Nathawad, R. Urata, B.A. Wooley, and D.A.B. Miller, "A 20 GHz bandwidth, 4b photoconductive-sampling time interleaved CMOS ADC," International Solid State Circuit Conference, Digest of Technical papers, pp.320–321, 2003.
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