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IEICE Transactions on Electronics 2008 E91-C(6):903-910; doi:10.1093/ietele/e91-c.6.903
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuits and Related SoC Integration Technologies - Papers

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

Yusuke OHTOMO1, Masafumi NOGAWA1, Kazuyoshi NISHIMURA1, Shunji KIMURA2, Tomoaki YOSHIDA2, Tomoaki KAWAMURA1, Minoru TOGASHI1 and Kiyomi KUMOZAKI2

1 The authors are with NTT Microsystem Integration Laboratories, NTT Corporation, Atsugi-shi, 243-0198 Japan. E-mail: ohtomo{at}aecl.ntt.co.jp, 2 The authors are with NTT Access Network Service Systems Laboratories, NTT Corporation, Chiba-shi, 261-0023 Japan.

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10 Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect level-varying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-µm CMOS process. It successfully operates at a data rate of 10.3125 Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2 ns with AC-coupling without a reset signal. The IC also demonstrates 1001 bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

Key Words: PON, burst, CDR, IC, CID


Manuscript received October 11, 2007.

References

[1] IEEE Std 802.3-2005, Section Five, Dec. 2005.

[2] http://www.ieee802.org/3/av/

[3] S. Kimura, A. Okada, J. Endo, H. Tanobe, Y. Suzuki, and M. Matsuoka, "10-Gbit/s burst-mode clock and data recovery units for optical packet-based systems," ECOC, vol.3, 8.2.5, Sept. 2002.

[4] H. Tagami, S. Kozaki, K. Nakura, S. Kohama, M. Nogami, and K. Motoshima, "A burst-mode bit-synchronization IC with large tolerance for pulse-width distortion for gigabit Ethernet PON," IEEE J. Solid-State Circuits, vol.41, no.11, pp.2555–2565, Nov. 2006.

[5] M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, "A 10 Gb/s burst-mode CDR IC in 0.13 µm CMOS," ISSCC Dig. Tech. Papers, pp.228–229, Feb. 2005.

[6] S. Kimura, M. Nogawa, K. Nishimura, T. Yoshida, K. Kumozaki, S. Nishihara, and Y. Ohtomo, "A 10-Gbit/s CMOS-burst-mode clock and data recovery IC for a WDM/TDM-PON access network," Proc. 17th Annu. Meeting IEEE Lasers and Electro-Optics Society (LEOS 2004), pp.310–311 July 2004.

[7] Y. Ohtomo, K. Nishimura, and M. Nogawa, "A 12.5 Gb/s parallel phase detection clock and data recovery circuit in 0.13-µm CMOS," IEEE J. Solid-State Circuits, vol.41, no.9, pp.2052–2057, Sept. 2006.

[8] C.F. Liang, S.C. Hwu, and S.I. Liu, "A multi-band burst-mode clock and data recovery circuit," IEICE Trans. Electron., vol.E90-C, no.4, pp.802–810, April 2006.

[9] C.F. Liang, S.C. Hwu, and S.I. Liu, "A 10 Gbps burst-mode CDR in 0.18 µm CMOS," Custom Integrated Circuits Conference (CICC) 16-2-1, pp.599–602, Sept. 2006.

[10] J. Lee and M. Liu, "A 20 Gb/s burst-mode CDR circuit using injection-locking technique," ISSCC Dig. Tech. Papers, pp.46–47, Feb. 2007.

[11] Q. Le, S.-G. Lee, Y.-H. Oh, H.-Y. Kang, and T.-H. Yoo, "A burst-mode receiver for 1.25-Gb/s Ethernet PON with AGC and internally created reset signal," IEEE J. Solid-State Circuits, vol.39, no.12, pp.2379–2388, Dec. 2004.

[12] B. Razavi, Design of Analog CMOS Integrated Circuits, p.516, McGraw-Hill, 2001.


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This Article
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