IEICE Transactions on Electronics

IEICE Transactions on Electronics 2008 E91-C(6):911-917; doi:10.1093/ietele/e91-c.6.911

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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuits and Related SoC Integration Technologies - Papers

A High Performance Spread Spectrum Clock Generator Using Two-Point Modulation Scheme

Yao-Huang KAO¹ and Yi-Bin HSIEH²

¹ The author is with the Department of Communication Engineering, Chung-Hua University, Hsin-Chu, Taiwan 300. E-mail: yhkao{at}chu.edu.tw, ² The author is with the Institute of Communication Engineering, National Chiao-Tung University Hsin-Chu, Taiwan 30050.

A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90 x 0.89 mm².

Key Words: phase-locked loops (PLLs), spread spectrum, and two-point, fractional-N

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Manuscript received October 17, 2007. Manuscript revised December 20, 2007.

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This Article Abstract Full Text (PDF) Alert me when this article is cited Alert me if a correction is posted Services Email this article to a friend Similar articles in this journal Alert me to new issues of the journal Add to My Personal Archive Download to citation manager Request Permissions Google Scholar Articles by KAO, Y.-H. Articles by HSIEH, Y.-B. Social Bookmarking          What's this?