Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Special Section on Analog Circuits and Related SoC Integration Technologies - Papers |
Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
1 The authors are with Kobe University, Kobe-shi, 657-8501 Japan. E-mail: kouji_ichikawa{at}denso.co.jp, 2 The authors are with DENSO CORPORATION, Kariya-shi, 448-8661 Japan.
Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.
Key Words: integrated circuit, electro magnetic interference, on-chip monitor, immunity
Manuscript received October 23, 2007. Manuscript revised December 26, 2007.
References
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