IEICE Transactions on Electronics - recent issues

Special Section on Advanced Processors Based on Novel Concepts in Computation

Shibata, T. — 2008-09-10

Ultra Dependable Processor

SAKAI, S., GOSHIMA, M., IRIE, H. — 2008-09-10

This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

A Simple Mechanism for Collapsing Instructions under Timing Speculation

SATO, T. — 2008-09-10

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.

Wide Dynamic Range Image Sensor with Polygonal-Line I/O Characteristic Adapted to Brightness Distribution of Objects

KAGAMI, S., SUZUKI, F., HAMAMOTO, T. — 2008-09-10

We propose a CMOS image sensor that realizes wide dynamic range imaging and nonlinear representation of I/O characteristics. The proposed image sensor controls the integration time for each pixel based on the brightness distribution of objects. The histogram at the end of the integration is estimated from the early intermediate photodiode values that are read out to an external circuit. Using the estimated histogram, the imaging parameters, which control the integration time pixel-by-pixel, are optimized in the external circuit. According to the imaging parameters, the intermediate photodiode value is compared with the threshold and reset to the starting value depending on the comparison result. These processes repeat several times. At the end of the integration, the photodiode value is reconstructed by using the imaging parameters. Then, wide dynamic range images with adapted I/O characteristics are obtained. We have fabricated a prototype with a size of 64 x 64 pixels using a 0.35-µm 2-poly 4-metal CMOS process. In this paper, we explain the principle of the proposed sensor and discuss the system architecture and its operation. The experimental results obtained using the prototype are also presented, and we verify its effectiveness.

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

2008-09-10

This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm² are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture

HARIYAMA, M., ISHIHARA, S., KAMEYAMA, M. — 2008-09-10

This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

An Energy Efficient Instruction Window for Scalable Processor Architecture

CHOI, M., MAENG, S. — 2008-09-10

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation

OKADA, N., KAMEYAMA, M. — 2008-09-10

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces

YOSHIKAWA, T., KOMATSU, Y., EBUCHI, T., HIRATA, T. — 2008-09-10

A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bi-directional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-spectrum-clocking (SSC) generator that reduces noise due to electromagnetic interference. A driver current control has been used for fast switching of data direction on ac-coupled interfaces. An adaptive bandwidth control has been used in a PLL to improve SCC significantly. A test chip has been fabricated and shows stable and bi-directional data communication with data rate of 162 to 972 Mbps through 20-m cable. Thanks to an optimum calibration of the SSC-PLL bandwidth, it reduces peak power at 33 kHz by –23 dB and provides 2% modulation at a data rate of 810 Mbps.

Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications

YOSHIKAWA, T., OGINO, T., NAGATA, M. — 2008-09-10

The novel low-power and low-EMI-noise current-mode data transceiver described here, which has a multilevel current driver in the transmitter (TX) and a low-input impedance I-V converter in the receiver (RX). No-feedback clock recovery in the RX is achieved by using multi-levels of a driving current from TX to specify a single bit boundary. The I-V converter suppresses voltage swing in the transmission line and generates a multi-level voltage signal according to the level of the submilliampere driving current it receives. Measurement shows a small voltage swing (20 mV) with 150-µA and 450-µA drive currents at 625 Mbps. The simple clock-recovery system and low driving current allow the transceiver to operate with a single 1.5-V power supply and use only 3.5 mW at 625 Mbps.

Near-Field to Far-Field Transformation for an Outdoor RCS Range

INASAWA, Y., KURODA, S., KAKIZAKI, K.-i., NISHIKAWA, H., YONEDA, N., MAKINO, S. — 2008-09-10

This paper presents the near-field to far-field transformation for an outdoor radar cross section (RCS) range. Direct measurement of the large actual target requires quite a long measurement range. The near-field to far-field RCS transformation method achieves the reduction of measurement range. However the non-uniformity of the incident electric field distribution on the target causes some errors in RCS prediction. We propose a novel near-field to far-field RCS transformation method that can be applied to an outdoor RCS measurement. The non-uniformity of the incident electric field distribution is successfully resolved by introducing the correction term of the ground bounce. We investigate the validity of the proposed method by the simulation and measurement.

Highly-Permissible Alignment Tolerance of Back-Illuminated Photo-Diode Array Attached with a Self-Aligned Micro Ball Lens

NISHIDE, K., IKEDA, K., SONG, X., WANG, S., NAKANO, Y. — 2008-09-10

Simulation and fabrication results on back-illuminated 4-channel photodiode (PD) array with a self-aligned micro ball lens are described. The channel pitch and diameter of each photosensitive area are 250µm and 40µm, respectively. Measured photocurrent is 1.92 times larger than that without a lens. Alignment tolerance between the single mode fiber (SMF) optical axis and the photodiode is improved from 21.2µm to 42.7µm. Moreover, the separation tolerance between the fiber and the lens is 210.5µm. These large tolerances agree with simulation results, demonstrating that the device configuration is suitable for receivers for multi-channel inter-connection. Frequency response and inter-channel cross talk are also discussed.

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

OU, H.-H., LIU, B.-D., CHANG, S.-J. — 2008-09-10

This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of –67.3 dB up to 250 MSample/s and a 0.8 VM_PP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration

SHINOHARA, H., NII, K., ONODERA, H. — 2008-09-10

An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random V_th variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low V_DD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as V_th, the W ratio, and V_DD were obtained. Maximum error measured in the V_DD range of 0.6–1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

Optical Properties of Copper in Chalcogenide Materials Used in Programmable Metallization Cell Devices

CHOI, H., NAM, K.-H., JU, L.-Y., CHUNG, H.-B. — 2008-09-10

Programmable Metallization Cell (PMC) Random Access Memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolytes. In this study, we investigate the nature of thin films formed by the photo doping of Cu into chalcogenide materials for use in programmable metallization cell devices. These devices rely on metal ion transport in the film so produced to create electrically programmable resistance states. The results imply that a Cu-rich phase separates owing to the reaction of Cu with free atoms from chalcogenide materials.

CMOS Cascode Source-Drain Follower for Monolithically Integrated Biosensor Array

NAKAZATO, K., OHURA, M., UNO, S. — 2008-09-10

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/°C. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3 µm x 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30°C and 100°C.

An LC-VCO Strongly Suppresses the AM-FM Conversion Caused by Varactor

SHIN, S. B., LEE, S.-G. — 2008-09-10

A differential LC-VCO that adopts a transformer with asymmetric turns-ratio has been proposed. The asymmetric turns-ratio of the transformer leads to the suppression of the AM to FM conversion which is caused by the 1/f noise of the current source transistor. The analysis of the proposed scheme and the improvement in phase noise compare to conventional CMOS LC-VCOs are described. The transformer used in proposed VCO occupies about 430x430 µm² of silicon area while the inductor in compared conventional VCO does 390x390 µm².

Evolutionary Synthesis of Practical Filters with Improved Group Delay Response

HOU, H.-S., HUANG, H.-M. — 2008-09-10

In this letter, a genetic programming method is used to synthesize filters. In order to improve the group delay characteristics, we propose a novel two-stage fitness function reflecting not only the frequency response but also the group delay characteristics of the evolved filters. We also deal with two practical design considerations, i.e., the filters include parasitic effects and are composed of elements with discrete values. The proposed method is applied to low-pass filter design cases. The experimental results show the method can effectively generate filters satisfying the design considerations and possessing improved group delay characteristics when compared with traditional filters.

Deadzone-Minimized Systematic Offset-Free Phase Detectors

KIM, Y.-S., SUH, Y., PARK, H.-J., SIM, J.-Y. — 2008-09-10

Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.

Special Section on Recent Development of Electromechanical Devices(Selected Papers from IS-EMD2007)

Umemura, S. — 2008-08-11

High Speed Electronic Connector Design: A Review of Electrical and Electromagnetic Properties of Passive Contact Elements -- Part 1

TIMSIT, R. S. — 2008-08-11

At high signal frequencies (i.e. in the GHz range), a connector must be considered as part of an electromagnetic transmission line. At these frequencies, the impedance characteristics of the connector stemming from the distributed inductance and capacitance of pins and the associated wiring, must be carefully controlled; insertion losses must be minimized and undesirable coupling between non-neighboring pins giving rise to crosstalk must be avoided to achieve optimal signal transmission. This paper reviews fundamental issues associated with the performance optimization of multi-conductor connector structures for high speed signal transmission. The paper complements an earlier publication that reviewed the major factors affecting electrical contact resistance at high frequencies [1].

Contact Resistance Characteristics of Improved Conductive Elastomer Contacts for Contaminated Printed Circuit Board in SO2 Environment

TAMAI, T., SAITOH, Y., HATTORI, Y., IKEDA, H. — 2008-08-11

Characteristics of conductive elastomer that is composed of silicone rubber and dispersed carbon black particles show conductive and elastic properties in one simple material. This material has been widely applied to make-break contacts of panel switches and connectors of liquid crystal panels. However, since surface state of the contact is very soft, it is difficult to remove contaminant films of contaminated opposite side contact surface and to obtain low contact resistance owing to break the film. This is an important problem to be solved not only for the application of make-break switching contact but also static connector contacts. This study has been conducted to examine some complex structures of the elastomer which indicate removal characteristics for contaminant films and low contact resistance. As specimens, six different types of elastomer contacts composed of different type of dispersed materials as carbon and metal fibers, metal mesh, and plated surfaces were used. The contacts of opposite side were Au and Sn plated contact surface on a printed circuit board (PCB) which is usually used in the static connector and make-break contacts. In order to contaminate contact surfaces of PCB, the surfaces were subjected to exposure in an SO₂ gas environment. The elastomeric contacts contained hard materials showed lower contact resistance than only dispersed carbon particles in the elastomer matrix for both contaminated PCB contact surfaces.

Micro-Structural Study of Fretting Contact Caused by the Difference of the Tin Plating Thickness

ITO, T., SAWADA, S., HATTORI, Y., SAITOH, Y., TAMAI, T., IIDA, K. — 2008-08-11

In recent years, there has been increasing demand to miniaturize wiring harness connectors in automobiles due to the increasing volume of electronic equipment and the reduction of the installation space allocated for the electronic equipment in automobiles for the comfort of the passengers. With this demand, contact failure caused by the fretting corrosion is expected to become a serious problem. In this report, we examined micro-structural observations of fretting contacts of two different tin plating thicknesses using Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) and so on. Based on the results, we compared the microstructure difference of fretting contact caused by the difference of the tin plating thickness.

Breaking Contact Phenomena of a Time-coordinated Non-arcing Relay

WAKATSUKI, N., HONMA, H. — 2008-08-11

VI time responses of a conventional electromagnetic relay during breaking contact operations were measured. In a conventional switching circuit, unstable contact resistance, irregular bouncing, and poor reproducibility were confirmed. Using a transient current switch circuit and two sharpened contact electrodes, bouncing during a breaking operation was suppressed, and unstable contact resistance changes and reproducibility of breaking operation were also improved.

A Study on Contact Spots of Earthquake Disaster Prevention Relays

WATANABE, Y., HIRAKAWA, Y. — 2008-08-11

This paper reports on the effect of switching action on the contact surfaces of earthquake disaster prevention relays. Large-scale earthquakes occur frequently in Japan and bring extensive damage with them, and fire caused by electrical equipments is one example of the serious damage which can occur. Earthquake sensors capable of maintaining a high level of reliability when earthquakes occur play an important role as a means of minimizing this damage. For this reason, we carried out observations by focusing on samples which had either been subjected to an electric current of 10 mA or 0.1 A. The samples of 10 mA exhibited low and constant contact resistance despite the addition of seismic motion, while the samples of 0.1 A samples exhibited varying contact resistance and damage on their contact spots resulting from the addition of seismic motion. The sample surfaces were then observed using an atomic force microscope (AFM) in tapping mode and a surface potential microscope (SPoM). As a result, we found that even the unused earthquake disaster prevention relay (standard sample) which had a surface lined with asperities on its parallel striations formed by irregular protrusions due to dust and other deposits. In addition, scanning the contact surface with the SPoM at the same potential revealed the occurrence of differences in surface potential which varied in response to the asperities on the striations.

3-D Finite Element Analysis of Dynamic Characteristics of Twin-Type Relay Interfered by Uniform Constant Magnetic Field

ZHAI, G., YANG, W., ZHOU, X. — 2008-08-11

Research on the electromagnetic compatibility of functional module composed of two independent electromagnetic relays in a hermetically sealed shell is the technical foundation for integration and miniaturization of electronic equipment in the future. In this paper, 3D finite element method (FEM) was used to analyze the dynamic characteristics of twin-type relay interfered by uniform constant magnetic field and identify the sensitive direction in which the relay was easily interfered. The models of twin-type relay in three working states were founded. Through simulation and analysis, it was found out how the operation time and electromagnetic torque of twin-type relay changed with the outer interfered magnetic field. When the relay was on the point of operation failure, the critical value of magnetic field was calculated through simulation. The simulation results of the dynamic characteristics of twin-type relay agree well with the experimental data. The conclusion in this paper is of great value for research on the electromagnetic compatibility of relay functional module.

Research on Effect of Ferromagnetic Material on the Critical Current of Bi-2223 Tape

WU, Y., RONG, M., LI, J., WANG, X. — 2008-08-11

In this paper we mainly focus on the effect of a ferromagnetic material on the critical current of Bi-2223 tape. The magnetic field distributions of tapes with several different layouts of a ferromagnetic material are investigated by calculation and the corresponding critical current is tested experimentally. The analysis indicates that the critical current of the tape can be improved effectively by laying the ferromagnetic material perpendicularly next to the tape edge. Furthermore, various other ferromagnetic parameters are also important for reducing the magnetic field induced by the current flowing through the tape.

An Integrated Calculation Method to Predict Arc Behavior

LI, X., CHEN, D. — 2008-08-11

The precision of magnetic field calculation is crucial to predict the arc behavior using magnetohydrodynamic (MHD) model. A integrated calculation method is proposed to couple the calculation of magnetic field and fluid dynamics based on the commercial software ANSYS and FLUENT, which especially benefits to take into account the existence of the ferromagnetic parts. An example concerning air arc is presented using the method.

The Relationship between Voltage and Duration of Short-Time Arc Generated by Slowly Breaking Silver Contact

KAYANO, Y., MIURA, H., MIYANAGA, K., INOUE, H. — 2008-08-11

Arc discharge generated by breaking electrical contact is considered as a main source of an undesired electromagnetic (EM) noise. To clarify mechanism of generation of the EM noise, feature extraction of bridge and short-time arc waveforms generated by slowly breaking Ag contact was discussed experimentally. The short-duration time arc before the ignition of the continuous metallic arc discharge was observed. The highest probability density voltage is defined as short-arc sustainable voltage (SASV). The relationship between SASV and duration of short-time arc was quantified experimentally. It is revealed that as the arc voltage of the short-time arc is higher, its duration becomes longer.

Study on Arc Generated by Opening Electromagnetic Relay Contacts in DC Low-Current Resistive Circuit with Constant Velocity

ZHAI, G., ZHOU, X. — 2008-08-11

An electrical arc is generated by opening the contacts of a relay when the current is above the minimum arc current in a circuit. A magneto-hydrodynamic (MHD) model was employed to simulate this dynamic arcing process. The distributions of arc parameters such as temperature, electrical field and magnetic flux density generated by opening the contacts in a circuit with a 5 A DC low current were obtained. The behaviors of the arc parameters with increasing gap length between the contacts were also simulated. The MHD model was then combined with structured dynamic layering, which is a dynamic meshing technique of computational fluid dynamics (CFD) to calculate the dynamic arcing process, and the arc parameters generated by opening the contacts in the circuit with a 5 A DC low current with a constant velocity were also obtained. It turned out that the computed time-varying contact voltage and arc duration agreed well with the test results. Thus, the validity of the simulation was demonstrated.

Simulation and Experimental Study of Arc Motion in a Low-Voltage Circuit Breaker Considering Wall Ablation

MA, Q., RONG, M., MURPHY, A. B., WU, Y., XU, T., YANG, F. — 2008-08-11

This paper focuses on the numerical and experimental investigations of the influence of two polymers (PA6 and POM) on the arc behavior during arc motion process. The mathematical model of 3-dimentional air arc plasma considering the ablation of lateral walls is built based on magnetic hydro-dynamics (MHD). By adopting the commercial computational fluid dynamics (CFD) package based on control-volume method, the above MHD model is solved and the distribution of temperature field, concentration field, flow field and electrical potential field in the arc chamber are calculated. The simulation results indicate that the vapor concentration behind the arc column is higher than that in front of the arc column because of the existence of "double vortices" in the arc chamber. The use of polymers causes the maximal arc voltage increase 16.2% with POM and 18.9% with PA6 in this case and causes the average arc velocity increase 15.8% with POM and 21.1% with PA6 in this case. The experiments are also carried out to study the influence of polymers on arc voltage and arc root position in the arc chamber during arc motion. The experimental results prove the validity of the numerical investigation.

Relationship between Arc Duration and Motion of Arc Spots for Break Arcs of Ag and Ag/ZnO Electrical Contacts

SEKIKAWA, J., SUGIO, T., KUBONO, T. — 2008-08-11

Break arcs are generated in a DC 42 V-10 A resistive circuit. The contact material is Ag or Ag/ZnO. The number of break operations is two hundreds for each contact material. The motion of break arcs is observed with a high-speed camera. Relationship between the dependence of arc duration on the number of operations and the motion of arc spots is investigated. The following results are shown. For Ag contacts the arc duration is almost constant independent to the number of break operations. For Ag/ZnO contacts, on the other hand, the arc duration changes irregularly to short (59 ms) or long (69 ms) arc-duration after 30th break operation. The moving range of arc spots on contact surfaces is broad for the case of short arc-duration and is narrow for the case of long arc-duration. The cause of the results for Ag/ZnO contacts is considered that the difference of the boiling points of Ag and ZnO leads to the porous structure on the contact surface.

Motion of Break Arcs Driven by External Magnetic Field in a DC42 V Resistive Circuit

SEKIKAWA, J., KUBONO, T. — 2008-08-11

Motion of break arcs driven by external magnetic field is observed using a high-speed camera. The magnetic field is applied with a permanent magnet. Experimental circuit is DC42 V-10 A resistive circuit. Material of electrical contacts is silver. Following results are shown. The break arcs are driven in the direction according to Lorentz force. The arc duration decreases with decrease of the distance between the electrical contacts and the magnet. When the external magnetic-flux density at the position of the break arc is lower than a certain value, the effect of the magnetic field to drive the break arc becomes ineffective to shorten the arc duration. The result is explained with a relationship between the motion of break arc and the distribution of the external magnetic field.

Effect of Back-Volume of Arc-Quenching Chamber on Arc Behavior

DAI, R., CHEN, D., LI, X., NIU, C., TONG, W., XIANG, H. — 2008-08-11

The gas-puffer effect has important effects on the interruption capability of a molded case circuit breaker (MCCB). In this paper, on the basis of a simplified model of an arc chamber with a single break, the effect of back-volume of an arc-quenching chamber on arc behavior in an MCCB is investigated. Firstly, using a 2-D optical-fiber arc-motion measurement system, experiments are performed to study the effect of back-volume on the arc-motion and gas pressure in an arc-quenching chamber. We demonstrate that the lower back-volume of the arc-quenching chamber is, the higher the pressure and the better the arc motion will be. Then, corresponding to the above experiments, the gas pressure inside the arc-quenching chamber is calculated using the integral conservation equation. The simulation results are consistent with the experimental results.

Time-Resolved Spectroscopic Temperature Measurement of Break Arcs in a D.C.42 V Resistive Circuit

SEKIKAWA, J., MORIYAMA, N., KUBONO, T. — 2008-08-11

In a D.C.42 V-10A resistive circuit, break arcs are generated between electrical contact pairs. The materials of the contact pairs are Ag, Ag/C 2wt%, Ag/SnO₂ 12wt%, and Ag/ZnO 12wt%. The arc spectral intensities are measured by a time-resolved spectroscopic temperature measurement system. The arc temperature is calculated from the spectral intensities by using the method of relative intensities of two spectra. The experimental results are as follows. The arc temperature gradually decreases with increase of the gap of electrical contacts. The ranges of arc temperature for Ag, Ag/C 2wt%, Ag/SnO₂ 12wt%, and Ag/ZnO 12wt% contacts pairs are 4500–11000 K, 4000–6000 K, 4000–7000 K, and 4000–11000 K, respectively.

Analysis and Optimization for a Contactor with Feedback Controlled Magnet System

LIU, Y., CHEN, D., NIU, C., JI, L., TONG, W. — 2008-08-11

In the optimum design of AC contactors, it is important to analyze the dynamic behavior. Moreover, movable contact and core bounces have remarkable effect on the lifetime of contactors. According to a new kind of contactor with feedback controlled magnet system, this paper builds two different sets of periodically inter-transferred equations to obtain the dynamic characteristics of the contactor. The equations describe the coupling of the electric circuit, electromagnetic field and mechanical system taking account of the influence of friction. Then, the paper gives an optimum design to the dimension and the duty ratio of the contactor' pulse modulated wave (PWM) under different exciting, and proves, by experiment and simulation, that the bounce time of the contactor working in the optimized duty ratio is much less than that of the general AC contactors.

Analysis and Optimization for the Operating Mechanism of Air Circuit Breaker

CHEN, D., JI, L., WANG, Y., LIU, Y. — 2008-08-11

This paper simulates the dynamic behavior of the operating mechanism of ACB, and analyzes factors influencing the mechanism's operating time. First, it builds a dynamic model for the mechanism with virtual prototype technology. Experiment validation is carried out to prove the correctness of the model. Based on this model, it puts emphasis on analyzing the influence of electro-dynamic repulsion force on the operating time of the mechanism. Simulation and experimental results show that after adding electric repulsion force to the model, the operating time is shortened about 1.1 ms. Besides the repulsion force, other influencing factors including the stiffness of opening spring, locations of every key axis, mass and centroidal coordinates of every mechanical part are analyzed as well. Finally, it makes an optimum design for the mechanism. After optimization, the velocity of operating mechanism is improved about 6.7%.

Thermal Analysis of AC Contactor Using Thermal Network Finite Difference Analysis Method

NIU, C., CHEN, D., LI, X., GENG, Y. — 2008-08-11

To predict the thermal behavior of switchgear quickly, the Thermal Network Finite Difference Analysis method (TNFDA) is adopted in thermal analysis of AC contactor in the paper. The thermal network model is built with nodes, thermal resistors and heat generators, and it is solved using finite difference method (FDM). The main circuit and the control system are connected by thermal resistors network, which solves the problem of multi-sources interaction in the application of TNFDA. The temperature of conducting wires is calculated according to the heat transfer process and the fundamental equations of thermal conduction. It provides a method to solve the problem of boundary conditions in applying the TNFDA. The comparison between the results of TNFDA and measurements shows the feasibility and practicability of the method.

A New Method to Evaluate the Short-Time Withstand Current for Air Circuit Breaker

XIANG, H., CHEN, D., LI, X., TONG, W. — 2008-08-11

Short-time withstand current is one of the crucial nominal parameters in air circuit breaker. A numerical method to evaluate the short-time withstand current is proposed. Cylindrical current carrying bridge is introduced to describe the contact spot between movable and fixed contacts. Taking into account the action of ferromagnetic splitter plates, the variation of the conductor properties with temperature and the variation of contact spot radius with the electro-dynamic repulsion force, a transient finite element calculation model is developed by coupling the electromagnetic field and thermal field. The loaded short circuit current is considered as the short-time withstand current once the highest temperature is near to the melting point of the contact material. It demonstrates that the method is useful to evaluate the performance of the air circuit breaker.

Research on Mechanical Fault Prediction Algorithm for Circuit Breaker Based on Sliding Time Window and ANN

WANG, X., RONG, M., QIU, J., LIU, D., SU, B., WU, Y. — 2008-08-11

A new type of algorithm for predicting the mechanical faults of a vacuum circuit breaker (VCB) based on an artificial neural network (ANN) is proposed in this paper. There are two types of mechanical faults in a VCB: operation mechanism faults and tripping circuit faults. An angle displacement sensor is used to measure the main axle angle displacement which reflects the displacement of the moving contact, to obtain the state of the operation mechanism in the VCB, while a Hall current sensor is used to measure the trip coil current, which reflects the operation state of the tripping circuit. Then an ANN prediction algorithm based on a sliding time window is proposed in this paper and successfully used to predict mechanical faults in a VCB. The research results in this paper provide a theoretical basis for the realization of online monitoring and fault diagnosis of a VCB.

Fundamental Measurement of Electromagnetic Field Radiated from a Coaxial Transmission Line Caused by Connector Contact Failure

HAYASHI, Y.-i., SONE, H. — 2008-08-11

When contact failure occurs in a connector in a coaxial HF signal transmission line, an electromagnetic field is radiated around the line. We have measured the electromagnetic field and examined the characteristics of such radiation. The results show that the radiation is related to the contact resistance and the symmetry of the distribution of contact points at the connector. When contact resistance is low, radiation is observed at resonant frequencies related to the length of the transmission line. If a connector has axially asymmetric contact points, its radiation is higher than that when the contact points are symmetric. We show that if contact points in a connector are axially symmetrical with resistance lower than 0.25 , the electromagnetic interference caused by the connector contact failure is as low as the background noise.

Special Section on Microelectronic Test Structures (ICMTS2007)

Mita, Y. — 2008-08-11

Leakage Current and Floating Gate Capacitor Matching Test

TIAN, W., TROGOLO, J. R., TODD, B. — 2008-08-11

Capacitor mismatch is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. In this paper we describe the impact of leakage current on the technique. The leakage can come from, for example, thin gate oxide MOSFETs or high dielectric constant capacitors in advanced technologies. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. Criteria for accurate capacitor systematic and random mismatch characterization are developed, and practical methods of increasing measurement accuracy are discussed.

Low-Capacitance and Fast Turn-on SCR for RF ESD Protection

LIN, C.-Y., KER, M.-D., MENG, G.-X. — 2008-08-11

With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESD-protected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well.

A Test Structure for Asymmetry and Orientation Dependence Analysis of CMOSFETs

2008-08-11

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of I_Dsat and I_Bmax with respect to the interchange of source and drain was examined. Although both I_Dsat and I_Bmax have similar channel orientation dependence, I_Bmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

2008-08-11

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Adaptive Impedance Matching System Using FPGA Processor for Efficient Control Algorithm

OBA, H., KIM, M., TAMAKI, R., ARAI, H. — 2008-08-11

The input impedance of an antenna fluctuates because of various usage conditions, which causes a mismatch between an internal circuit and an antenna. An automatic matching system solves this problem, then this paper presents a reconfigurable impedance tuner that has a set of fixed capacitors controlled by switching p-i-n diodes. A fast control algorithm for selecting the appropriate conditions of an impedance tuner is proposed and mounted on FPGA to demonstrate the performance.

A CMOS Low Dropout Regulator with Extended Stable Region for the Effective Series Resistance of the Output Capacitor

PAN, H.-I, CHEN, C.-L. — 2008-08-11

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

A Single Input Change Test Pattern Generator for Sequential Circuits

LIANG, F., LEI, S., SHAO, Z. — 2008-08-11

An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.

Quadrature Hartley VCO and Injection-Locked Frequency Divider

JANG, S.-L., CHANG, C.-W., WU, S.-C., LEE, C.-F., TSAI, L.-y., HUANG, J.-F. — 2008-08-11

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is –124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is –185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

Design of a 0.5 V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources

WANG, J., LEE, T.-Y., KIM, D.-G., MATSUOKA, T., TANIGUCHI, K. — 2008-08-11

This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization

2008-08-11

We have developed a compact double-gate metal-oxide-semiconductor field-effect transistor model for circuit simulation considering the volume inversion effect by solving the Poisson equation explicitly. It is verified that applied voltage dependence of the calculated potential values both at the surface and at the center of the silicon layer reproduce 2 dimensional device simulation results for any device structure, confirming the validity of the model for device optimization.

Special Section on Heterostructure Microelectronics with TWHM 2007

Waho, T. — 2008-07-15

Development of High-Frequency GaN HFETs for Millimeter-Wave Applications

HIGASHIWAKI, M., MIMURA, T., MATSUI, T. — 2008-07-15

This paper describes the device fabrication process and characteristics of AlGaN/GaN heterostructure field-effect transistors (HFETs) aimed for millimeter-wave applications. We developed three novel techniques to suppress short-channel effects and thereby enhance high-frequency device characteristics: high-Al-composition and thin AlGaN barrier layers, SiN passivation by catalytic chemical vapor deposition, and sub-100-nm Ti-based gates. The Al_0.4Ga_0.6N/GaN HFETs with a gate length of 30 nm had a maximum drain current density of 1.6 A/mm and a maximum transconductance of 402 mS/mm. The use of these techniques led to a current-gain cutoff frequency of 181 GHz and a maximum oscillation frequency of 186 GHz.

Normally-Off AlGaN/GaN HEMTs with Thin InGaN Cap Layer

ITO, M., KISHIMOTO, S., NAKAMURA, F., MIZUTANI, T. — 2008-07-15

We have fabricated AlGaN/GaN HEMTs with a thin InGaN cap layer to implement normally-off HEMTs with a small extrinsic source resistance. The key idea is to employ the polarization-induced field in the InGaN cap layer, by which the conduction band is raised leading to the normally-off operation. Fabricated HEMT with an In_0.2Ga_0.8N cap layer with a thickness of 5 nm showed normally-off operation with a threshold voltage of 0.4 V and a maximum transconductance of 85 mS/mm for the device with a 1.9-µm-long gate. By etching-off the In_0.2Ga_0.8N cap layer at the region except under the gate using gate and ohmic electrodes as etching masks, the sheet resistance has decreased from 2.7 to 0.75 k/, and the maximum transconductance has increased from 85 to 130 mS/mm due to a reduction of the extrinsic source resistance. The transconductance was increased from 130 to 145 mS/mm by annealing the devices at 250°C for 20 minutes in a N₂ atmosphere.

AlN/GaN Metal Insulator Semiconductor Field Effect Transistor on Sapphire Substrate

SEO, S., GHOSE, K., ZHAO, G. Y., PAVLIDIS, D. — 2008-07-15

AlN/GaN Metal Insulator Semiconductor Field Effect Transistors (MISFETs) were designed, simulated and fabricated. DC, S-parameter and power measurements were also performed. Drift-diffusion simulations using DESSIS compared AlN/GaN MISFETs and Al₃₂Ga₆₈N/GaN Heterostructure FETs (HFETs) with the same geometries. The simulation results show the advantages of AlN/GaN MISFETs in terms of higher saturation current, lower gate leakage and higher transconductance than AlGaN/GaN HFETs. First results from fabricated AlN/GaN devices with 1 µm gate length and 200 µm gate width showed a maximum drain current density of ~380 mA/mm and a peak extrinsic transconductance of 85 mS/mm. S-parameter measurements showed that current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max) were 5.85 GHz and 10.57 GHz, respectively. Power characteristics were measured at 2 GHz and showed output power density of 850 mW/mm with 23.8% PAE at V_DS = 15 V. To the authors knowledge this is the first report of a systematic study of AlN/GaN MISFETs addressing their physical modeling and experimental high-frequency characteristics including the power performance.

Enhancement-Mode n-Channel GaN MOSFETs Using HfO2 as a Gate Oxide

SUGIURA, S., KISHIMOTO, S., MIZUTANI, T., KURODA, M., UEDA, T., TANAKA, T. — 2008-07-15

We have fabricated enhancement-mode n-channel GaN MOSFETs with overlap gate structure on a p-GaN using thick HfO₂ as a gate insulator. The maximum transconductance of 23 mS/mm which is 4 times larger, to our knowledge, than the best-reported value of the normally-off GaN MOSFETs with SiO₂ gate oxide has been obtained.

Investigation on Current Collapse of AlGaN/GaN HFET by Gate Bias Stress

AO, J.-P., YAMAOKA, Y., OKADA, M., HU, C.-Y., OHNO, Y. — 2008-07-15

The mechanism of current collapse of AlGaN/GaN heterojunction field-effect transistors (HFETs) was investigated by gate bias stress with and without illumination. It is clarified that there are two positions where negative charges accumulate, at the gate edge and in the bulk epi-layer. In the gate-edge mode, the charge comes either through the passivation film or the AlGaN layer, depending on the resistance of the films. Reduction of leakage current in the passivation film will be important to suppress the surface-related collapse.

Effects of a Thermal CVD SiN Passivation Film on AlGaN/GaN HEMTs

2008-07-15

In AlGaN/GaN high electron mobility transistors (HEMTs), drain current reduction by current collapse phenomenon is a big obstacle for a high efficient operation of power amplifier application. In this study, we investigated the effects of SiN passivation film quality on the electrical characteristics of AlGaN/GaN HEMTs. First, we conducted some experiments to investigate the relationship between electrical characteristics of AlGaN/GaN HEMTs and various conditions of SiN passivation film by plasma enhanced chemical vapor deposition (PE-CVD). We found that both gate current leakage and current collapse were improved simultaneously by SiN passivation film deposited by optimized condition of NH₃ and SiH₄ gas flow. It is found that the critical parameter in the optimization is a I_N-H/I_Si-H ratio measured by Fourier transforms infrared spectroscopy (FT-IR) spectra. Next, a thermal CVD SiN was applied to the passivation film to be investigated from the same point of view, because a thermal CVD SiN is well known to have good quality with low hydrogen content and high I_N-H/I_Si-H ratio. We confirmed that the thermal CVD SiN passivation could improve much further both of the gate leakage current and the current collapse in AlGaN/GaN-HEMTs. Furthermore, we tried to apply the thermal CVD SiN to the gate insulator in MIS (Metal Insulator Semiconductor) structure of AlGaN/GaN HEMTs. The thermal CVD SiN passivation was more suitable for the gate insulator than PE-CVD SiN passivation in a view of reducing current collapse phenomena. It could be believed that the thermal CVD SiN film is superior to the PE-CVD SiN film to achieve good passivation and gate insulator film for AlGaN/GaN HEMTs due to the low hydrogen content and the high I_N-H/I_Si-H ratio.

Low Leakage Current ITO Schottky Electrodes for AlGaN/GaN HEMTs

MATSUDA, K., KAWASAKI, T., NAKATA, K., IGARASHI, T., YAEGASSI, S. — 2008-07-15

To reduce the gate leakage current of AlGaN/GaN HEMTs, we selected ITO/Ni/Au for Schottky electrodes and Schottky characteristics were compared with those of Ni/Au electrodes. ITO/Ni/Au and Ni/Au electrodes were deposited by vacuum evaporation and annealed at 350°C in nitrogen atmosphere. From the I-V evaluation results of ITO/Ni/Au electrodes, forward and reverse leakage currents were reduced. Schottky characteristics of ITO/Ni/Au electrodes were also improved compared to these of Ni/Au electrodes. In addition, substantial decrease of leakage currents was confirmed after the annealing of HEMTs with ITO/Ni/Au electrodes. This may be explained that ITO/AlGaN interface state became lower by the annealing. By the temperature dependence of I-V curves, clear dependence was confirmed for the gates with ITO/Ni/Au electrodes. On the other hand, small dependence was observed for those with Ni/Au electrodes. From these results, tunnel leakage currents were dominant for the gates with Ni/Au electrode. Thermal emission current was dominant for the gates with ITO/Ni/Au electrode. The larger temperature dependence was caused that ITO/AlGaN interface states were smaller than those for Ni/Au electrode. It was suggested that suppressed AlGaN Schottky barrier thinning was caused by the surface defect donors, then tunneling leakage currents were decreased. We evaluated HEMT characteristics with ITO/Ni/Au electrode and Ni/Au electrode. I_{d max} and G_{m max} were similar characteristics, but V_th with ITO/Ni/Au electrode was shifted +0.4 V than that with Ni/Au electrode due to the higher Schottky barrier. It was confirmed to have a good pinch-off currents and low gate leakage currents by ITO/Ni/Au electrodes.

A Study on Ohmic Contact to Dry-Etched p-GaN

HU, C.-Y., AO, J.-P., OKADA, M., OHNO, Y. — 2008-07-15

Low-power dry-etching process has been adopted to study the influence of dry-etching on Ohmic contact to p-GaN. When the surface layer of as-grown p-GaN was removed by low-power SiCl₄/Cl₂-etching, no Ohmic contact can be formed on the low-power dry-etched p-GaN. The same dry-etching process was also applied on n-GaN to understand the influence of the low-power dry-etching process. By capacitance-voltage (C-V) measurement, the Schottky barrier heights (SBHs) of p-GaN and n-GaN were measured. By comparing the change of measured SBHs on p-GaN and n-GaN, it was suggested that etching damage is not the only reason responsible for the degraded Ohmic contacts to dry-etched p-GaN and for Ohmic contact formatin, the original surface layer of as-grown p-GaN have some special properties, which were removed by dry-etching process. To partially recover the original surface of as-grown p-GaN, high temperature annealing (1000°C 30 s) was tried on the SiCl₄/Cl₂-etched p-GaN and Ohmic contact was obtained.

A GaAs SOI HEMT Fabricated by Fluidic Self-Assembly and Its Application to an RF-Switch

MAEZAWA, K., SOGA, I., KISHIMOTO, S., MIZUTANI, T., AKAMATSU, K. — 2008-07-15

The heterogeneous integration of GaAs HEMTs on a polyimide-covered AlN ceramic substrate was demonstrated using a fluidic self-assembly (FSA) technique. We used thin device blocks for the FSA, which have various advantages. In particular, they can reduce the drain-source capacitance C_ds of the assembled HEMTs if the substrate has a low dielectric constant. This is a novel kind of semiconductor-on-insulator (SOI) technology. The dc and RF properties of the GaAs HEMTs on the polyimide/AlN substrate were studied and the reduction of C_ds was confirmed. This technique was successfully applied to the SPDT switch, where a low C_ds is essential for good isolation.

Current Status and Future Prospects of SiC Power JFETs and ICs

ZHAO, J. H., SHENG, K., ZHANG, Y., SU, M. — 2008-07-15

This paper will review the development of SiC power devices especially SiC power junction field-effect transistors (JFETs). Rationale and different approaches to the development of SiC power JFETs will be presented, focusing on normally-OFF power JFETs that can provide the highly desired fail-save feature for reliable power switching applications. New results for the first demonstration of SiC Power ICs will be presented and the potential for distributed DC-DC power converters at frequencies higher than 35 MHz will be discussed.